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![FPGA-based systolic deconvolution architecture for upsampling [PeerJ]](https://dfzljdn9uc3pi.cloudfront.net/2022/cs-973/1/fig-1-full.png "FPGA-based systolic deconvolution architecture for upsampling [PeerJ]")
FPGA-based systolic deconvolution architecture for upsampling [PeerJ]
FluTAS: A GPU-accelerated finite difference code for multiphase flows - ScienceDirect
FluTAS: A GPU-accelerated finite difference code for multiphase flows - ScienceDirect
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